1. Field of the Invention
This invention is directed to a method for annealing the source and drain regions of an integrated transistor device. More specifically, the invention can be used to melt and recrystallize the source and drain regions of an integrated transistor device to activate the junction thereof for proper electrical performance.
2. Description of the Related Art
As scaling of integrated devices progresses to below one-tenth of a micrometer (0.1 .mu.m) with gate oxide thicknesses below thirty Angstroms (30 .ANG.), severe problems are created by depletion of polysilicon gates, gate resistance and gate leakage. These problems have generated renewed interest in the use of metals for gates and alternative oxides for use as gate dielectric layers in processes for forming integrated devices. However, the use of metals for the gate electrode poses serious problems. Many processes for forming integrated devices involve a high-temperature anneal step in which the substrate is heated, often for extended periods of time, to activate the source and drain regions. This sort of extended thermal treatment is extremely destructive to most types of metals or dielectric stacks (i.e., multilayer structures that include conductive and dielectric layers) used for gate electrodes. Present proposals to overcome this problem add significant complexity to the process for forming an integrated device. It would thus be desirable to provide a relatively simplified method for forming an integrated device in which activation of the source and drain regions can be performed without adverse impact on the gate electrode.
One method for annealing source and drain regions without subjecting metal gates to destructive heating relies upon the use of relatively intense radiant energy generated by a laser or lamp, for example. However, the use of radiant energy for annealing the junction of an integrated device poses its own problems. By way of background to explain these problems, FIG. 1 shows a cross-section of an integrated device, in this case a metal-insulator-semiconductor field-effect transistor (MISFET) 1 that is formed in an active region of the substrate that is bounded and electrically isolated by field isolation region 3. A well region 4 is formed in the active region by introducing dopants into the semiconductor substrate 2. A gate region 7 is fabricated on the substrate 2 by forming a gate insulator layer 8 and a gate conductor layer 9, and patterning these layers by selective etching, for example, so that these layers overlie a limited portion of the active region that is to serve as the channel region of the integrated device 1. Dopants of opposite type as that of the well region 4 are implanted in the active region to form the source region 5 and drain region 6 on opposite sides of the gate region 7. To melt and recrystallize the source and drain regions 5, 6 for activation, a laser or lamp is used to generate radiant energy 10 which is directed to the source and drain regions. As shown in FIG. 1, the fact that the gate region 7 extends higher than the source and drain regions 5, 6 causes the radiant energy to be partially blocked in those portions of the source and drain regions 5, 6 immediately adjacent the gate region 7. Also, the relatively sharp features at the edges of gate region 7 cause the radiant energy 10 to diffract and generate interference patterns on the source and drain regions adjacent the gate. These shadowing and interference effects, represented by numeral 11 in FIG. 1, reduce the amount of radiant energy in the source and drain regions 5, 6 near the gate region's edge as compared to portions of the source and drain regions that are relatively distant from the gate region's edge. The reduction of radiant energy absorption in the portions of the source and drain regions 5, 6 adjacent the gate region 7 make it relatively difficult to melt such portions of the source and drain regions. Furthermore, at the portions of the source and drain regions 5, 6 adjacent the field isolation regions 3, the relatively poor thermal conductivity of the field isolation regions as well as optical interference effects, can lead to excessive melting beyond the desired source and drain boundaries into the substrate 2, a problem that can adversely affect electrical isolation of the device and significantly degrade the device's performance. Thus, the fluence of the radiant energy used for the annealing step must be controlled within a relatively narrow range to affect melting of the edges of the source and drain regions 5, 6 both near the field isolation region 3 and the gate region 7 without melting the underlying substrate 2. Simultaneous achievement of these constraints in previous methods for forming an integrated device is typically very difficult, if not impossible. It would be desirable to provide a method in which annealing of the source and drain regions of a transistor can be performed with radiant energy so as not to melt the metal gate conductor layer 9 while achieving relatively uniform melting of the source and drain regions 5, 6 to enhance the process margin available for successful performance of the method beyond that attainable with previous technologies.